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Figure 2 | BMC Bioinformatics

Figure 2

From: FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

Figure 2

Hardware design for Chebyshev log(x) approximation. Shown in the figure: (a) the input value x is resolved into one of the sixteen sets of coefficients using a comparison network (synchronization delays not shown), (b) powers of x are computed (D blocks represent delays), and (c) the Chebyshev polynomial is computed. The total latency of this circuit is 45 cycles and 50 cycles for single- and double-precision on the Virtex-2 Pro FPGA, and 39 and 48 cycles on the Virtex-6 FPGA.

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