Figure 5
From: FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Design for scaling and likelihood evaluation computation. The four-input adder is implemented using a 2-stage binary adder tree. This pipeline has a total latency of 213 cycles on a Virtex-2 Pro FPGA and 227 cycles on a Virtex-6 FPGA (251 and 261 when including the conditional probability pipeline that feeds this pipeline), including single-to-double precision conversion between the normalization and likelihood pipelines (not shown).