TY - JOUR AU - Luo, Ruibang AU - Cheung, Jeanno AU - Wu, Edward AU - Wang, Heng AU - Chan, Sze-Hang AU - Law, Wai-Chun AU - He, Guangzhu AU - Yu, Chang AU - Liu, Chi-Man AU - Zhou, Dazong AU - Li, Yingrui AU - Li, Ruiqiang AU - Wang, Jun AU - Zhu, Xiaoqian AU - Peng, Shaoliang AU - Lam, Tak-Wah PY - 2015 DA - 2015/04/23 TI - MICA: A fast short-read aligner that takes full advantage of Many Integrated Core Architecture (MIC) JO - BMC Bioinformatics SP - S10 VL - 16 IS - 7 AB - Short-read aligners have recently gained a lot of speed by exploiting the massive parallelism of GPU. An uprising alterative to GPU is Intel MIC; supercomputers like Tianhe-2, currently top of TOP500, is built with 48,000 MIC boards to offer ~55 PFLOPS. The CPU-like architecture of MIC allows CPU-based software to be parallelized easily; however, the performance is often inferior to GPU counterparts as an MIC card contains only ~60 cores (while a GPU card typically has over a thousand cores). SN - 1471-2105 UR - https://doi.org/10.1186/1471-2105-16-S7-S10 DO - 10.1186/1471-2105-16-S7-S10 ID - Luo2015 ER -