Figure 4From: FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methodsDesign for conditional probability computation. In the accelerator design, this design is replicated four times (for each nucleotide) to implement Equation 1. The latency of this pipeline is 38 cycles on the Virtex-2 Pro FPGA and 34 cycles on the Virtex-6 FPGA, based on floating-point cores from Xilinx Core Generator.Back to article page