Table 3 Performance Results for SSE3 and fast log approximation.
From: FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Average SW node processing time (μs) | Average HW node processing time (μs) and speedup relative to SW | ||||||
|---|---|---|---|---|---|---|---|
Dataset | Non-root | Root node | Average | Ave. HW time/node @ 165 MHz (μs) | Speedup vs. SW | Ave. HW time/node @ 310 MHz (μs) | Speedup vs. SW |
m993 | 16.1 | 43.1 | 17.1 | 6.6 | 2.6 | 3.5 | 4.9 |
m1319 | 20.7 | 54.2 | 22.7 | 9.0 | 2.5 | 4.8 | 4.7 |
m346 | 41.1 | 118.0 | 44.0 | 9.6 | 4.6 | 5.1 | 8.7 |
m1038 | 46.3 | 119.4 | 47.0 | 13.0 | 3.6 | 6.9 | 6.8 |
m1485 | 61.5 | 166.2 | 65.5 | 19.0 | 3.4 | 10.1 | 6.5 |
m4056 | 193.6 | 560.3 | 198.2 | 58.7 | 3.4 | 31.2 | 6.4 |
m3631 | 199.6 | 563.9 | 205.9 | 83.0 | 2.5 | 44.1 | 4.7 |